1. Field of the Invention
Embodiments of the invention relate generally to synchronizing clocks over packet switched networks, such as the Internet. More specifically, but not by way of limitation, embodiments of the invention relate to minimizing the effects of queuing delays on a transmitted timing signal.
2. Description of the Related Art
The advent of low-cost broadband Internet connections has created a demand for packet-switched networks, including the Internet itself, for the transport of audio, video, and other time-sensitive real-time signals. Systems that receive live or real-time signals over packet-switched networks, such as live audio and video streaming servers, video conferencing systems, or distributed real-time computing systems, require access to a local time clock that can maintain phase and frequency synchronization to the remote transmitter's clock. Such a synchronized local clock provides a reference against which a time stamp, either embedded within the real-time signal itself or stamped within an encapsulating packet, can determine an appropriate play-out time for an audio or video rendering engine at the receiver. However, the large queuing delays that arise in packet-switched networks, such as the Internet, induce significant packet timing jitter. Such jitter has traditionally been an impediment to live Internet streaming.
Traditionally, Internet streaming media applications employ large amounts of spooling, on the order of 10 seconds to over a minute, to handle Internet jitter. Unfortunately, live interactive audio and video applications require that end-to-end latency be under 500 milliseconds, and preferably less than 100 milliseconds. The reduction of latency to such low levels requires the use of precision clock synchronization. Precision clock synchronization enables the minimization of jitter queue size. The problem is that traditional clock recovery mechanisms for clock synchronization, such as phase-locked loops (PLLs), generally cannot handle such large Internet jitter levels.
The technical literature contains many references to phase and frequency locked loops and other clock recovery techniques for synchronizing a local clock to a remote clock with high precision and low jitter, provided that the jitter of the input signal does not exceed the design parameters of the clock recovery mechanism.
Unfortunately, congestion in packet-switched networks induces queuing delays that often add substantial jitter to these real-time signals. (We define jitter as the maximum variation in inter-packet arrival time.) The resulting jitter may impair the operation of standard clock recovery mechanisms and rendering engines. Consequently, standard real-time clock recovery mechanisms often do not work well when synchronizing to a timing signal transmitted across a packet-switched network, such as the Internet.
Buffering the input packet stream can eliminate jitter problems at the rendering engine. Buffering incoming packets with an input queue can eliminate network packet jitter, provided that the input queue is large enough to absorb all of the jitter, and that the packets are read out of the input queue at a constant rate that matches the average rate at which incoming packets are received. As long as this jitter removal queue neither overflows with packet loss, nor underflows to interrupt the smooth flow of data, then the rendering engine can function properly. However to prevent queue underflow or overflow, the use of such a de-jitter queue requires a synchronized local play-out clock that substantially tracks the frequency and phase of the remote clock generating the packetized data. Here again, jitter can impair the ability of a clock recovery mechanism to provide a synchronized clock for the jitter removal buffer.
One recent patent titled, “Minimizing the effect of jitter upon the quality of service operation of networked gateway devices” (U.S. Pat. No. 6,704,329, Martin, G.), claims a method to reduce the effects of network jitter that involves filtering a phase error by a minimum-delay filter to generate a control signal to control the frequency of a variable-frequency oscillator as part of a clock recovery mechanism. While this may produce a stable, low-jitter recovered clock from a high-jitter timing signal, it does not guarantee a low phase error. The slow response of a filtered control signal to adjust the frequency of a reference oscillator is generally a slow process that may allow significant phase drift in the reference clock. Furthermore, if the goal is to simply remove jitter so that a standard PLL can later recover the clock, then the additional step of generating a digital control signal is superfluous and adds implementation cost and complexity.